(1) Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly relates to semiconductor integrated circuit devices in which memory circuits, logic circuits, and other circuits are combined together.
(2) Description of Related Art
In recent years, with an increase in the scale and degree of integration of semiconductor integrated circuit devices, circuit operations have been becoming more complicated. In particular, for products using chargers, such as cell phones, the time during which a battery can be used has been demanded to be increased. To respond to this demand, a clock gating technique has been suggested in which the power consumption of a semiconductor integrated circuit device is reduced in the following manner: When a functional circuit that operates in synchronization with a clock signal is not being used in the integrated circuit device during an operation of the integrated circuit device, the clock signal is prevented from being supplied to the functional circuit, thereby ceasing an operation of the functional circuit. The use of such a clock gating technique can suppress a redundant circuit operation. This can avoid a problem concerning power consumption.
However, as process rules of semiconductor integrated circuit devices become finer, the leakage current through transistors has been increasing. Also when a semiconductor integrated circuit device is not operating, redundant power is consumed due to the leakage current. This has become a serious problem.
To cope with this, in recent years, a power gating (power shutdown) technique has been suggested in which power is supplied to a plurality of related functional circuits formed in the semiconductor integrated circuit device in units of functional circuit blocks composed of the plurality of functional circuits or the power supply thereto is interrupted in units of the functional circuit blocks, thereby reducing the power consumed due to leakage current passing through some of the functional circuit blocks that are not in use.
Disclosed, for example, in Japanese Unexamined Patent Publication No. 2003-132683 are a semiconductor integrated circuit device in which power is supplied to functional circuits in units of functional circuit blocks obtained by integrating functional circuits, such as logic circuits and memory circuits, or the power supply thereto is interrupted in units of the functional circuit blocks, thereby reducing the power consumed due to leakage current, and a method for driving the same (power supply method).
According to the method, the power supply to circuits that are not being used in the semiconductor integrated circuit device can be interrupted in units of functional circuit blocks. This permits a reduction in redundant power consumed due to leakage current.
However, in a known semiconductor integrated circuit device and a known method for driving the same, power is shut off at only one point (power supply interruption element) between a power source and functional circuit blocks. Therefore, the power supply and power supply interruption can be executed only in units of the functional circuit blocks. All of functional circuits included in each functional circuit block are seldom used at the same time, and each of operating ones of the functional circuit blocks usually include functional circuits that are not in use. In view of the above, in the known semiconductor integrated circuit device in which the power supply and power supply interruption are executed in units of the functional circuit blocks, power is supplied also to some of the functional circuits that are not in use. This causes leakage current passing through the circuit.
In a case where functional circuits distributed in each of functional circuit blocks are formed with interconnects for supplying power to the associated functional circuits to control the power supply conditions for each functional circuit, a signal delay is caused due to the differences among interconnects in resistance and parasitic capacitance, and a voltage drop or any other problem is caused due to high interconnect resistance. For this reason, the power supply to the functional circuits and the interruption of the power supply cannot be efficiently executed simply by providing each interconnect with a point at which power can be shut off. For example, the time at which power is supplied to the functional circuits and the time at which the power supply thereto is interrupted vary among the functional circuits included in the functional circuit block, and the supply voltage varies thereamong.